A conventional MRAM using a thin film of metallic magnetic material includes two types, one type utilizing a giant magnetoresistance effect (GMR) and the other type utilizing a tunneling magnetoresistance effect (TMR). An electrical resistance between two magnetic layers located adjacent to one another through a nonmagnetic layer is relatively low when the magnetization orientations of the two magnetic layers are parallel, and is increased when the magnetization orientations of the two magnetic layers are anti-parallel. These phenomenons are utilized to differentiate “1” and “0”, respectively. In a writing operation, a given current is supplied to each of a bit line and a word line to invert the magnetization orientation of the magnetic layer with a higher coercive force in a memory cell at the intersection between the bit and word lines by a current magnetic field. The “1” or “0” is set according to the inverted magnetization orientation. In a reading operation, the magnetization orientation of the magnetic layer with a lower coercive force is inverted by a current magnetic field to determine the “1” or “0” based on the effect of GMR or TMR.
The MRAM using a GMR element is more easily prepared. In addition, the GMR element itself is a conductor, and thereby a plural number of the GMR elements can be connected in series with each other to facilitate increase in its memory capacity. However, if N-memory cells exist along a single bit line, each of the memory cells will receive only 1/N of a signal voltage. Thus, an excessive increase in the number N causes difficulties in the reading operation due to disappearance of the signal voltage into noises. Moreover, in the GMR element having a low resistance, a signal voltage itself is inherently low, and thereby it is required to provide a reading amplifier having a larger amplification capacity, which leads to increase in cost and chip size. This is a problem in applications to customer devices, and consequently the GMR memory is used only as military and space devices under extremely limited conditions.
A series connection as in the GMR element cannot be applied to the MRAM using a TMR element due to a high resistance of the TMR element, and a parallel connection has to be used therefor. Typically, in this type of MRAM, a MOS transistor is combined with the TMR element to form a memory cell, because in the absence of the MOS transistor, a current applied to bit and word lines will be supplied to not only a selected memory cell but also the remaining cells.
The MOS transistor is required to carry out a switching function essential in selecting an intended memory element. Thus, the memory size of the MRAM is determined by the dimensional size of the MOS transistor. This is a realistic major issue in connection with achievement of a larger-capacity MRAM, and one of factors obstructive to practical use of the MRAM.
The memory cell has a configuration similar to a DRAM (Dynamic Random-Access Memory), in which the TMR element is used in place of a capacitor. While the fundamental configuration of the memory cell is also similar to a FeRAM (Ferroelectric Random-Access Memory), one bit in the FeRAM is composed of two transistors and two ferroelectric elements to cope with an unsolved problem about large variations. Thus, the memory cell size per bit is increased, and thereby it is difficult to achieve high-integration.
At present, a TMR element using a thin film of metallic magnetic material has a magnetoresistance change rate (MR rate) of about 50%. This MR rate is not varied depending on the dimensions of the TMR element. In a DRAM, a capacitance is lowered as the dimensions of an element are reduced. While the MR rate in the MRAM is not varied depending on the dimensions of the TMR element, a capacitance in a DRAM is lowered as the dimensions of an element are reduced.
The MRAM allows for high-speed access because the spin-flip therein occurs within one nanosecond. Specifically, the MRAM allows writing/reading operations to be performed at a higher speed than that in a DRAM, and in a non-destructive manner.
Further, the thin film for the TMR element can be formed at room temperatures. This eliminates the risk of causing the destruction of the MOS transistor during the film forming process. In contrast, one of reasons for difficulties in achieving a larger-capacity FeRAM is in that a ferroelectric film can be formed only at a high temperature of 500° C. or more.
The MRAM also has a feature of allowing a number of rewriting operations without problems. In addition, the MRAM is usable in nuclear reactors and outer space because of its excellent nuclear radiation resistance.
As above, the MRAM can perform writing/reading operations at a high speed in a non-volatile manner, and facilitate increase in its memory capacity. However, in a conventional MRAM using a thin film of metallic ferromagnetic material, when a memory cell size is reduced, the intensity of a current magnetic field required for magnetization inversion has to be increased. This is a problem in developing a larger-capacity MRAM, and one of factors obstructive to practical use of the MRAM.
While the variation of a TMR value can be controlled to fall within 2%, the magnetic field for magnetization inversion is largely varied. Further, as to a heat stability of the TMR element, while a maximum MR rate is achieved at an annealing temperature of 300° C., the conventional MRAM has to be typically subjected to a heat treatment at a temperature of 400° C. in a hydrogen atmosphere to recover damages in a CMOS transistor due to microfabrication and/or patterning of metal wirings. During this heat treatment, the MR rate of the TMR element becomes zero. Thus, it is required to improve the heat resistance of the TMR element or reduce the temperature for the heat treatment of the CMOS transistor.
There is another problem about microfabrication for use in a thin film of metallic magnetic material. Specifically, while the thin film is microfabricated through physical cutting by means of lithography and ion milling ion as a technique for research, such a technique cannot be applied to large-scale productions. It is essential for the large-scale production of MRAM devices to develop a production technique based on a dry etching process or chemical reaction etching which is used for semiconductors. For example, a recent prior art related to such MRAM devices includes the following Patent Publications 1, 2 and 3.
Patent Publication 1: Japanese Patent Laid-Open Publication No. 11-135857 (Patent No. 3050189)
Patent Publication 2: Japanese Patent Laid-Open Publication No. 2000-106462
Patent Publication 3: WO 01/024289 (domestic re-publication of PCT international publication for patent applications)